1 tm file number 4401.8 huf76145p3, huf76145s3s 75a, 30v, 0.0045 ohm , n-channel, logic level ultrafet power mosfets these n-channel power mosfets are manufactured using the innovative ultrafet process. this advanced process technology achieves the lowest possible on-resistance per silicon area, resulting in outstanding performance. this device is capable of withstanding high energy in the avalanche mode and the diode exhibits very low reverse recovery time and stored charge. it was designed for use in applications where power ef?iency is important, such as switching regulators, switching converters, motor drivers, relay drivers, low-voltage bus switches, and power management in portable and battery-operated products. formerly developmental type ta76145. symbol features logic level gate drive 75a, 30v ultra low on-resistance, r ds(on) = 0.0045 ? temperature compensating pspice model temperature compensating saber model thermal impedance spice model thermal impedance saber model peak current vs pulse width curve uis rating curve related literature - tb334, ?uidelines for soldering surface mount components to pc boards packaging jedec to-220ab jedec to-263ab ordering information part number package brand huf76145p3 to-220ab 76145p huf76145s3s to-263ab 76145s note: when ordering, use the entire part number. add the suffix t to obtain the to-263ab variant in tape and reel, e.g., HUF76145S3ST. d g s drain source gate drain (flange) gate source drain (flange) data sheet august 2000 caution: these devices are sensitive to electrostatic discharge. follow proper esd handling procedures. ultrafet?is a registered trademark of intersil corporation. pspice?is a registered trademark of microsim corporation. saber is a trademark of analogy, inc. 1-888-intersil or 321-724-7143 | intersil and design is a trademark of intersil corporation. | copyright ?intersil corporation 2000
2 absolute maximum ratings t c =25 o c , unless otherwise speci?d units drain to source voltage (note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v dss 30 v drain to gate voltage (r gs = 20k ? ) (note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v dgr 30 v gate to source voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v gs 16 v drain current continuous (t c = 25 o c, v gs = 10v) (figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i d continuous (t c = 100 o c, v gs = 5v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i d continuous (t c = 100 o c, v gs = 4.5v) (figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i d pulsed drain current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .i dm 75 75 75 figure 4 a a a pulsed avalanche rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . e as figure 6 power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . p d derate above 25 o c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 2.17 w w/ o c operating and storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . t j , t stg -40 to 150 o c maximum temperature for soldering leads at 0.063in (1.6mm) from case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .t l package body for 10s, see techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . t pkg 300 260 o c o c caution: stresses above those listed in ?bsolute maximum ratings may cause permanent damage to the device. this is a stress only rating and operatio n of the device at these or any other conditions above those indicated in the operational sections of this speci?ation is not implied. note: 1. t j = 25 o c to 150 o c. electrical speci?ations t a = 25 o c, unless otherwise specified parameter symbol test conditions min typ max units off state specifications drain to source breakdown voltage bv dss i d = 250 a, v gs = 0v (figure 12) 30 - - v zero gate voltage drain current i dss v ds = 25v, v gs = 0v - - 1 a v ds = 25v, v gs = 0v, t c = 150 o c - - 250 a gate to source leakage current i gss v gs = 16v - - 100 na on state specifications gate to source threshold voltage v gs(th) v gs = v ds , i d = 250 a (figure 11) 1 - 3 v drain to source on resistance r ds(on) i d = 75a, v gs = 10v (figures 9, 10) - 0.0035 0.0045 ? i d = 75a, v gs = 5v (figure 9) - 0.0043 0.0058 ? i d = 75a, v gs = 4.5v (figure 9) - 0.0046 0.0065 ? thermal specifications thermal resistance junction to case r jc (figure 3) - - 0.46 o c/w thermal resistance junction to ambient r ja to-220 and to-263 - - 62 o c/w switching specifications (v gs = 4.5v) turn-on time t on v dd = 15v, i d ? 75a, r l = 0.20 ? , v gs = 4.5v, r gs = 2.5 ? (figure 15) - - 255 ns turn-on delay time t d(on) -26-ns rise time t r - 145 - ns turn-off delay time t d(off) -35-ns fall time t f -39-ns turn-off time t off - - 110 ns huf76145p3, huf76145s3s
3 switching specifications (v gs = 10v) turn-on time t on v dd = 15v, i d ? 75a, r l = 0.20 ? , v gs = 10v, r gs = 2.2 ? (figure 16) - - 110 ns turn-on delay time t d(on) -16-ns rise time t r -57-ns turn-off delay time t d(off) -53-ns fall time t f -38-ns turn-off time t off - - 135 ns gate charge specifications total gate charge q g(tot) v gs = 0v to 10v v dd = 15v, i d ? 75a, r l = 0.20 ? i g(ref) = 1.0ma (figure 14) - 130 156 nc gate charge at 5v q g(5) v gs = 0v to 5v - 73 88 nc threshold gate charge q g(th) v gs = 0v to 1v - 4.65 5.6 nc gate to source gate charge q gs - 12.30 - nc gate to drain ?iller?charge q gd - 40.00 - nc capacitance specifications input capacitance c iss v ds = 25v, v gs = 0v, f = 1mhz (figure 13) - 4900 - pf output capacitance c oss - 2520 - pf reverse transfer capacitance c rss - 560 - pf electrical speci?ations t a = 25 o c, unless otherwise specified (continued) parameter symbol test conditions min typ max units source to drain diode speci?ations parameter symbol test conditions min typ max units source to drain diode voltage v sd i sd = 75a - - 1.25 v reverse recovery time t rr i sd = 75a, di sd /dt = 100a/ s - - 115 ns reverse recovered charge q rr i sd = 75a, di sd /dt = 100a/ s - - 255 nc typical performance curves figure 1. normalized power dissipation vs case temperature figure 2. maximum continuous drain current vs case temperature t a , ambient temperature ( o c) power dissipation multiplier 0 0 25 50 75 100 150 0.2 0.4 0.6 0.8 1.0 1.2 125 0 20 40 60 80 25 50 75 100 125 150 175 i d , drain current (a) t c , case temperature ( o c) v gs = 10v v gs = 4.5v huf76145p3, huf76145s3s
4 figure 3. normalized maximum transient thermal impedance figure 4. peak current capability figure 5. forward bias safe operating area note: refer to intersil application notes an9321 and an9322. figure 6. unclamped inductive switching capability typical performance curves (continued) 0.1 1 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 0.01 2 t, rectangular pulse duration (s) z jc , normalized single pulse notes: duty factor: d = t 1 /t 2 peak t j = p dm x z jc x r jc + t c p dm t 1 t 2 duty cycle - descending order 0.5 0.2 0.1 0.05 0.01 0.02 thermal impedance 100 1000 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 5000 50 i dm , peak current (a) t, pulse width (s) transconductance may limit current in this region t c = 25 o c i = i 25 175 - t c 150 for temperatures above 25 o c derate peak current as follows: v gs = 10v v gs = 5v 10 100 1000 1 10 100 100 s 10ms 1ms v ds , drain to source voltage (v) i d , drain current (a) limited by r ds(on) area may be operation in this t j = max rated t c = 25 o c single pulse 1 10 100 100 0.1 1000 10 i as , avalanche current (a) t av , time in avalanche (ms) t av = (l)(i as )/(1.3*rated bv dss - v dd ) if r = 0 if r 0 t av = (l/r)ln[(i as *r)/(1.3*rated bv dss - v dd ) +1] starting t j = 25 o c starting t j = 150 o c 0.01 huf76145p3, huf76145s3s
5 figure 7. transfer characteristics figure 8. saturation characteristics figure 9. drain to source on resistance vs gate voltage and drain current figure 10. normalized drain to source on resistance vs junction temperature figure 11. normalized gate threshold voltage vs junction temperature figure 12. normalized drain to source breakdown voltage vs junction temperature typical performance curves (continued) 0 2345 1 0 60 120 i d , drain current (a) v gs , gate to source voltage (v) 150 o c -40 o c 25 o c pulse duration = 80 s duty cycle = 0.5% max v dd = 15v 150 90 30 0 30 60 0 234 90 i d , drain current (a) v ds , drain to source voltage (v) v gs = 3.5v v gs = 3v 150 1 120 v gs = 4v v gs = 4.5v v gs = 5v v gs = 10v pulse duration = 80 s duty cycle = 0.5% max t c = 25 o c 10 20 0 4 v gs , gate to source voltage (v) 2610 8 i d = 75a i d = 50a i d = 25a r ds(on) , drain to source on resistance (m ? ) 5 15 pulse duration = 80 s duty cycle = 0.5% max 0.6 1.2 1.5 1.8 -60 0 60 120 normalized drain to source t j , junction temperature ( o c) on resistance 180 0.9 pulse duration = 80 s duty cycle = 0.5% max v gs = 10v, i d = 75a -60 0 60 120 0.4 0.6 1.0 1.4 normalized gate t j , junction temperature ( o c) threshold voltage v gs = v ds , i d = 250 a 180 0.8 1.2 1.2 1.1 1.0 0.9 -60 0 60 120 t j , junction temperature ( o c) normalized drain to source breakdown voltage i d = 250 a 180 huf76145p3, huf76145s3s
6 figure 13. capacitance vs drain to source voltage note: refer to intersil application notes an7254 and an7260. figure 14. gate charge waveforms for constant gate current figure 15. switching time vs gate resistance figure 16. switching time vs gate resistance typical performance curves (continued) c oss 8000 4000 0 0 5 15 25 c, capacitance (pf) 6000 v ds , drain to source voltage (v) 2000 30 c iss c rss 10 20 v gs = 0v, f = 1mhz c iss = c gs + c gd c rss = c gd c oss c ds + c gd 10 8 6 4 0 v gs , gate to source voltage (v) v dd = 15v 2 120 160 0 q g , gate charge (nc) 40 i d = 75a i d = 50a i d = 25a waveforms in descending order: 80 200 20 30 40 50 0 1200 800 400 0 10 switching time (ns) r gs , gate to source resistance ( ? ) v gs = 4.5v, v dd = 15v, i d = 75a, r l = 0.20 ? 1000 600 t d(off) t d(on) t r t f 400 20 30 40 50 0 1000 800 600 0 10 switching time (ns) r gs , gate to source resistance ( ? ) v gs = 10v, v dd = 15v, i d = 75a, r l = 0.20 ? 200 t d(on) t d(off) t f t r test circuits and waveforms figure 17. unclamped energy test circuit figure 18. unclamped energy waveforms t p v gs 0.01 ? l i as + - v ds v dd r g dut vary t p to obtain required peak i as 0v v dd v ds bv dss t p i as t av 0 huf76145p3, huf76145s3s
7 figure 19. gate charge test circuit figure 20. gate charge waveforms figure 21. switching time test circuit figure 22. switching time waveform test circuits and waveforms (continued) r l v gs + - v ds v dd dut i g(ref) v dd q g(th) v gs = 1v q g(5) v gs = 5v q g(tot) v gs = 10 v ds v gs i g(ref) 0 0 v gs r l r gs dut + - v dd v ds v gs t on t d(on) t r 90% 10% v ds 90% 10% t f t d(off) t off 90% 50% 50% 10% pulse width v gs 0 0 huf76145p3, huf76145s3s
8 pspice electrical model subckt huf76145 2 1 3 ; rev 6 apr98 ca 12 8 7.75e-9 cb 15 14 7.45e-9 cin 6 8 4.47e-9 dbody 7 5 dbodymod dbreak 5 11 dbreakmod dplcap 10 5 dplcapmod ebreak 11 7 17 18 33.5 eds 14 8 5 8 1 egs 13 8 6 8 1 esg 6 10 6 8 1 evthres 6 21 19 8 1 evtemp 20 6 18 22 1 it 8 17 1 ldrain 2 5 1.00e-9 lgate 1 9 2.60e-9 lsource 3 7 1.10e-9 kgate lsource lgate 0.0085 mmed 16 6 8 8 mmedmod mstro 16 6 8 8 mstromod mweak 16 21 8 8 mweakmod rbreak 17 18 rbreakmod 1 rdrain 50 16 rdrainmod 0.59e-3 rgate 9 20 0.898 rldrain 2 5 10 rlgate 1 9 26 rlsource 3 7 11 rslc1 5 51 rslcmod 1e-6 rslc2 5 50 1e3 rsource 8 7 rsourcemod 2.20e-3 rvthres 22 8 rvthresmod 1 rvtemp 18 19 rvtempmod 1 s1a 6 12 13 8 s1amod s1b 13 12 13 8 s1bmod s2a 6 15 14 13 s2amod s2b 13 15 14 13 s2bmod vbat 22 19 dc 1 eslc 51 50 value={(v(5,51)/abs(v(5,51)))*(pwr(v(5,51)/(1e-6*750),3))} .model dbodymod d (is = 6.01e-12 ikf = 20 rs = 1. 72e-3 trs1 = 1.01e-3 trs2 = 1.21e-6 cjo = 8.41e-9 tt = 4.84e-8 m = 0.45 ) .model dbreakmod d (rs = 6.80e-2 trs1 = 1.12e-3 trs2 = 1.25e-6 ) .model dplcapmod d (cjo = 4.25e-9 is = 1e-30 n = 10 m = 0.61) .model mmedmod nmos (vto = 1.74 kp = 5.00 is = 1e-30 n = 10 tox = 1 l = 1u w = 1u rg = 0.898) .model mstromod nmos (vto = 2.10 kp = 245 is = 1e-30 n = 10 tox = 1 l = 1u w = 1u) .model mweakmod nmos (vto = 1.48 kp = 0.10 is = 1e-30 n = 10 tox = 1 l = 1u w = 1u rg = 8.98 rs= 0.1) .model rbreakmod res (tc1 = 1.01e-3 tc2 = 1.07e-7) .model rdrainmod res (tc1 = 1.58e-2 tc2 = 3.76e-5) .model rslcmod res (tc1 = 1.02e-4 tc2 = -1.13e-4) .model rsourcemod res (tc1 = 0 tc2 = 0) .model rvthresmod res (tc1 = -2.73e-3 tc2 = -1.01e-5) .model rvtempmod res (tc1 = -1.50e-3 tc2 = 1.25e-6) .model s1amod vswitch (ron = 1e-5 roff = 0.1 von = -6.00 voff= -1.50) .model s1bmod vswitch (ron = 1e-5 roff = 0.1 von = -1.50 voff= -6.00) .model s2amod vswitch (ron = 1e-5 roff = 0.1 von = 0.00 voff= 0.45) .model s2bmod vswitch (ron = 1e-5 roff = 0.1 von = 0.45 voff= 0.00) .ends note: for further discussion of the pspice model, consult a new pspice sub-circuit for the power mosfet featuring global temperature options ; ieee power electronics specialist conference records, 1991, written by william j. hepp and c. frank wheatley. 18 22 + - 6 8 + - 5 51 + - 19 8 + - 17 18 6 8 + - 5 8 + - rbreak rvtemp vbat rvthres it 17 18 19 22 12 13 15 s1a s1b s2a s2b ca cb egs eds 14 8 13 8 14 13 mweak ebreak dbody rsource source 11 7 3 lsource rlsource cin rdrain evthres 16 21 8 mmed mstro drain 2 ldrain rldrain dbreak dplcap eslc rslc1 10 5 51 50 rslc2 1 gate rgate evtemp 9 esg lgate rlgate 20 + - + - + - 6 huf76145p3, huf76145s3s
9 saber electrical model rev 6 apr 1998 template huf76145 n2, n1, n3 electrical n2, n1, n3 { var i iscl d..model dbodymod = (is = 6.01e-12, cjo = 8.41e-9, tt = 4.84e-8, m = 0.45) d..model dbreakmod = () d..model dplcapmod = (cjo = 4.25e-9, is = 1e-30, n = 10, m = 0.61) m..model mmedmod = (type=_n, vto = 1.74, kp = 5.00, is = 1e-30, tox = 1) m..model mstrongmod = (type=_n, vto = 2.10, kp = 245, is = 1e-30, tox = 1) m..model mweakmod = (type=_n, vto = 1.48, kp = 0.10, is = 1e-30, tox = 1) sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -6.0, voff = -1.5) sw_vcsp..model s1bmod = (ron = 1e-5, roff = 0.1, von = -1.5, voff = -6.0) sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = 0.0, voff = 0.45) sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.45, voff = 0.0) c.ca n12 n8 = 7.75e-9 c.cb n15 n14 = 7.45e-9 c.cin n6 n8 = 4.47e-9 d.dbody n7 n71 = model=dbodymod d.dbreak n72 n11 = model=dbreakmod d.dplcap n10 n5 = model=dplcapmod i.it n8 n17 = 1 l.ldrain n2 n5 = 1.00e-9 l.lgate n1 n9 = 2.60e-9 l.lsource n3 n7 = 1.10e-9 k.k1 i(l.lgate) i(l.lsource) = l(l.lgate), l(l.lsource), 0.0085 m.mmed n16 n6 n8 n8 = model=mmedmod, l = 1u, w = 1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l = 1u, w = 1u m.mweak n16 n21 n8 n8 = model=mweakmod, l = 1u, w = 1u res.rbreak n17 n18 = 1, tc1 = 1.01e-3, tc2 = 1.07e-7 res.rdbody n71 n5 = 1.72e-3, tc1 = 1.01e-3, tc2 = 1.21e-6 res.rdbreak n72 n5 = 6.80e-2, tc1 = 1.12e-3, tc2 = 1.25e-6 res.rdrain n50 n16 = 0.59e-3, tc1 = 1.58e-2, tc2 = 3.76e-5 res.rgate n9 n20 = 0.898 res.rldrain n2 n5 = 10 res.rlgate n1 n9 = 26 res.rlsource n3 n7 = 11 res.rslc1 n5 n51 = 1e-6, tc1 = 1.02e-4, tc2 = -1.13e-4 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 2.20e-3, tc1 = 0, tc2 = 0 res.rvtemp n18 n19 = 1, tc1 = -1.50e-3, tc2 = 1.25e-6 res.rvthres n22 n8 = 1, tc1 = -2.73e-3, tc2 = -1.01e-5 spe.ebreak n11 n7 n17 n18 = 33.50 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 spe.evthres n6 n21 n19 n8 = 1 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc = 1 equations { i (n51->n50) + = iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/750))** 3)) } } 18 22 + - 6 8 + - 19 8 + - 17 18 6 8 + - 5 8 + - rbreak rvtemp vbat rvthres it 17 18 19 22 12 13 15 s1a s1b s2a s2b ca cb egs eds 14 8 13 8 14 13 mweak ebreak dbody rsource source 11 7 3 lsource rlsource cin rdrain evthres 16 21 8 mmed mstro drain 2 ldrain rldrain dbreak dplcap iscl rslc1 10 5 51 50 rslc2 1 gate rgate evtemp 9 esg lgate rlgate 20 + - + - + - 6 rdbody rdbreak 72 71 huf76145p3, huf76145s3s
10 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?ation. intersil semiconductor products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/or spec ifications at any time with- out notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is b elieved to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of th ird parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see web site www.intersil.com sales of?e headquarters north america intersil corporation p. o. box 883, mail stop 53-204 melbourne, fl 32902 tel: (321) 724-7000 fax: (321) 724-7240 europe intersil sa mercure center 100, rue de la fusee 1130 brussels, belgium tel: (32) 2.724.2111 fax: (32) 2.724.22.05 asia intersil ltd. 8f-2, 96, sec. 1, chien-kuo north, taipei, taiwan 104 republic of china tel: 886-2-2515-8508 fax: 886-2-2515-8369 spice thermal model rev aug 2000 huf76145t ctherm1 th 6 6.3e-3 ctherm2 6 5 1.5e-2 ctherm3 5 4 2.0e-2 ctherm4 4 3 3.0e-2 ctherm5 3 2 8.0e-2 ctherm6 2 tl 1.5e-1 rtherm1 th 6 5.0e-3 rtherm2 6 5 1.8e-2 rtherm3 5 4 5.0e-2 rtherm4 4 3 8.5e-2 rtherm5 3 2 1.0e-1 rtherm6 2 tl 1.1e-1 saber thermal model saber thermal model huf76145t template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 = 6.3e-3 ctherm.ctherm2 6 5 = 1.5e-2 ctherm.ctherm3 5 4 = 2.0e-2 ctherm.ctherm4 4 3 = 3.0e-2 ctherm.ctherm5 3 2 = 8.0e-2 ctherm.ctherm6 2 tl = 1.5e-1 rtherm.rtherm1 th 6 = 5.0e-3 rtherm.rtherm2 6 5 = 1.8e-2 rtherm.rtherm3 5 4 = 5.0e-2 rtherm.rtherm4 4 3 = 8.5e-2 rtherm.rtherm5 3 2 = 1.0e-1 rtherm.rtherm6 2 tl = 1.1e-1 } rtherm4 rtherm6 rtherm5 rtherm3 rtherm2 rtherm1 ctherm4 ctherm6 ctherm5 ctherm3 ctherm2 ctherm1 tl 2 3 4 5 6 th junction case huf76145p3, huf76145s3s
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